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Scalability and Design-Space Analysis of a 1T-1MTJ Memory Cell for STT-RAMs

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6 Author(s)
Richard Dorrance ; Department of Electrical Engineering, University of California, Los Angeles, CA, USA ; Fengbo Ren ; Yuta Toriyama ; Amr Amin Hafez
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We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the statistical variation of an MTJ's critical switching current and resistance. The sensitivity of the design space to different design parameters is also analyzed for the scaling of both the MTJ and the underlying transistor technology. A design flow, using a sensitivity-based analysis and an MTJ switching model based on the Landau-Lifshitz-Gilbert equation, is proposed to optimize design margins for gigabit-scale memories. Design points for improved yield, density, and memory performance are extracted from MTJ-compatible complementary metal-oxide-semiconductor (CMOS) technologies for 90-, 65-, 45-, and 32-nm processes. Predictive technology models are used to explore the future scalability of STT-RAMs in upcoming 22- and 16-nm technology nodes. Our analysis shows that, to achieve Flash-like densities ( <; 6F2) in advanced CMOS technologies, aggressive scaling of the critical switching current density will be required.

Published in:

IEEE Transactions on Electron Devices  (Volume:59 ,  Issue: 4 )