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Design and evaluation of variable stages pipeline processor with low-energy techniques

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4 Author(s)
Nakabayashi, T. ; Dept. of Inf. Eng., Mie Univ., Tsu, Japan ; Sasaki, T. ; Ohno, K. ; Kondo, T.

Enhancement of mobile computers requires high-performance computing with low-energy consumption. Variable stages pipeline (VSP) architecture, which reduces energy consumption and improves execution time by dynamically unifying the pipeline stages, is proposed to achieve this requirement. A VSP processor uses a special pipeline register called a latch D-flip-flop selector-cell (LDS-cell) that unifies the pipeline stages and prevents glitch propagation caused by stage unification under low-energy mode. The design of the fabricated VLSI of a VSP processor chip on 0.18 m CMOS technology is presented. An evaluation shows that the VSP processor consumes 13 less energy than a conventional one.

Published in:

Computers & Digital Techniques, IET  (Volume:6 ,  Issue: 1 )