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Leakage Characterization of 10T SRAM Cell

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2 Author(s)
A. Islam ; Department of ECE, BIT, Mesra, Ranchi, Jharkhand, India ; M. Hasan

This paper presents a technique for designing a low-power and variability-aware SRAM cell. The cell achieves low power dissipation due to its series-connected tail transistor and read buffers, which offer a stacking effect. This paper studies the impact of process, voltage, and temperature (PVT) variations on most of the design metrics of the SRAM cell and compares the results with standard 6T, 9T, and ST10T (Schmitt trigger based) SRAM cells.

Published in:

IEEE Transactions on Electron Devices  (Volume:59 ,  Issue: 3 )