FPGA design of a truncated SVD based receiver for the detection of SEFDM signals

This work presents the hardware design of a novel algorithm using Field Programmable Gate Arrays (FPGAs) for the detection of Spectrally Efficient Frequency Division Multiplexing (SEFDM) signals. Previous work has shown that a sub-optimal Truncated Singular Value Decomposition (TSVD) approach is well-suited for use in SEFDM systems. TSVD offers a targeted reduction in complexity while outperforming linear detectors, such as Zero Forcing (ZF) and Minimum Mean Squared Error (MMSE), in terms of Bit Error Rate (BER). This is the first time a hardware design for the TSVD algorithm has been devised for implementation on an FPGA device using Very high speed integrated circuit Hardware Description Language (VHDL). Results show excellent fixed-point performance which are comparable to existing floating-point computer-based simulations. The optimal parameters required to achieve this outcome combined with their effect on system performance are identified. The impact of finite FPGA resources against performance gain is also examined.