Referenced Items are not available for this document.
A low power Delay Locked Loop based Clock and Data Recovery circuit has been designed in this paper. A standby filter is a novel feature in this design. Level tracking technique is used for data recovery. The circuit is designed using Verilog HDL. The layout of the circuit is generated and verified using Cadence SoC Encounter. Total die area and total dynamic power dissipation of the circuit is 0.01mm2 and 799.8643μW respectively at 1.8V power supply.
Published in:
India Conference (INDICON), 2011 Annual IEEE
Date of Conference: 16-18 Dec. 2011
- Page(s):
- 1 - 4
- Print ISBN:
- 978-1-4577-1110-7
- INSPEC Accession Number:
- 12506823
- Conference Location :
- Hyderabad
- Digital Object Identifier :
- 10.1109/INDCON.2011.6139507
- Product Type:
- Conference Publications
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