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A low power Delay Locked Loop based Clock and Data Recovery circuit has been designed in this paper. A standby filter is a novel feature in this design. Level tracking technique is used for data recovery. The circuit is designed using Verilog HDL. The layout of the circuit is generated and verified using Cadence SoC Encounter. Total die area and total dynamic power dissipation of the circuit is 0.01mm2 and 799.8643μW respectively at 1.8V power supply.