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Power consumption during test can be significantly higher than during normal functional mode. This paper presents a low power Automated Test Pattern Generation (ATPG) flow for managing capture power in today's power critical designs. It introduces a novel method for sequentially enabling the on-chip clock controllers to generate accurate low power ATPG patterns respecting the power specifications of the design. The effectiveness of the method is demonstrated on several industrial designs that show up power issues during test mode.
Test Conference (ITC), 2011 IEEE International
Date of Conference: 20-22 Sept. 2011