Referenced Items are not available for this document.
To develop a new processor for embedded applications, we must first characterize the processor, in order to take appropriate trade-off between performance and chip area. This study presents a DS-HIE architecture, which achieve high performance on a limited chip area by using the appropriate bit-width.
Published in:
SoC Design Conference (ISOCC), 2011 International
Date of Conference: 17-18 Nov. 2011
- Page(s):
- 187 - 190
- E-ISBN :
- 978-1-4577-0710-0
- Print ISBN:
- 978-1-4577-0709-4
- INSPEC Accession Number:
- 12496040
- Conference Location :
- Jeju
- Digital Object Identifier :
- 10.1109/ISOCC.2011.6138679
- Product Type:
- Conference Publications
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