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Design consideration for reconfigurable processor DS-HIE — Trade-off between performance and chip area

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2 Author(s)
Tanigawa, K. ; Grad. Sch. of Inf. Sci., Hiroshima City Univ., Hiroshima, Japan ; Hironaka, T.

To develop a new processor for embedded applications, we must first characterize the processor, in order to take appropriate trade-off between performance and chip area. This study presents a DS-HIE architecture, which achieve high performance on a limited chip area by using the appropriate bit-width.

Published in:

SoC Design Conference (ISOCC), 2011 International

Date of Conference:

17-18 Nov. 2011