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Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems

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5 Author(s)
Jozwik, K. ; Grad. Sch. of Inf. Sci., Nagoya Univ., Nagoya, Japan ; Tomiyama, H. ; Edahiro, M. ; Honda, S.
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In the field of embedded systems, where evergrowing demands for short time-to-market, low cost, low power, high performance and increased flexibility are prevalent, modern FPGAs (Field Programmable Gate Arrays) are gaining wider popularity in a variety of applications. Moreover, capability of DPR (Dynamic Partial Reconfiguration) found in some of these devices can further help in meeting these demands. With the increasing trend to integrate multiple functions into a single device, programming difficulty, well known for FPGAs, and the complexity of management of dynamically reconfigurable resources drive the need for an OS (Operating System). The OS would provide a well-defined computing model abstracting details and capacity of the underlying hardware. This paper familiarizes the readers with the topic of DPR, pointing out its advantages and limitations, and a related HW (hardware) multitasking computing model. Furthermore, it presents results of an ongoing research on an efficient hardware platform for HW multitasking and an accompanying OS extension which facilitates its programmability and serves as a base for fully fledged DPR embedded systems.

Published in:

SoC Design Conference (ISOCC), 2011 International

Date of Conference:

17-18 Nov. 2011