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The time spent to design mixed hardware-software embedded systems is proportioned to their complexity. We present a highly efficient method that make use of simulators in order to find a pareto-solution between execution time and hardware area for mixed hardware-software embedded systems. Our method generates the minimum possible number of mappings in order to reduce the number of simulations. The exploration starts with two system mappings as initial pareto-solution. Then it repeats three steps, the generation of mappings, the simulation of generated mappings, and the update of the pareto-solution with the results of simulations. The experimental results show that our method is notably efficient and is able to find a pareto-solution with few errors compared to the complete search method.