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A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS

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8 Author(s)
Norifumi Kanemaru ; Solutions Research Laboratory, Tokyo Institute of Technology, 4259-S2-14 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan ; Sho Ikeda ; Tatsuya Kamimura ; Sang yeop
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This paper proposes a low-phase-noise ring-VCO-based frequency multiplier with a new subharmonic direct injection locking technique that only uses a time-delay cell and four MOS transistors. Since the proposed technique behaves as an exclusive OR and can double the reference signal frequency, it increases phase correction points and achieves low phase noise characteristic across the wide output frequency range. The frequency multiplier was fabricated by using 65 nm Si CMOS process. Measured 1-MHz-offset phase noise at 6.34 GHz with reference signals of 528 MHz was -113dBc/Hz.

Published in:

SoC Design Conference (ISOCC), 2011 International

Date of Conference:

17-18 Nov. 2011