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As CMOS technology is scaled down more aggressively; the reliability mechanism (or aging effect) caused by progressive gate oxide breakdown, also called time dependent dielectric breakdown (TDDB), has become a major reliability concern. With the present of TDDB, it is difficult to control the ON current of the MOSFET device. In addition, nanoscale CMOS circuits suffer from increased gate leakage current and power consumption. In this paper, the TDDB effects on delay and power of the nanoscale CMOS circuits are analyzed using inverter chains and ISCAS85 benchmark circuits, which are designed using 45-nm CMOS predictive technology model. Finally, we discuss post-silicon adaptive tuning techniques to compensate the TDDB impact on the CMOS circuits.