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The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technology) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60% greater than that of the previous write circuit and is sufficient for the proper write operation.