Scheduled System Maintenance on May 29th, 2015:
IEEE Xplore will be upgraded between 11:00 AM and 10:00 PM EDT. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Analysis of SRAM hierarchical bitlines for optimal performance and variation tolerance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Qi Li ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore ; Kim, T.T.

Hierarchical bitlines improve performance and power consumption due to the reduced bitline capacitance associated with read/write operations. This paper analyzes hierarchical bitlines and provides optimal solutions for maximum performance and minimum variance. Simulation results demonstrate that the optimized 2-stage hierarchical bitlines in the conventional 6T and 8T SRAMs improve the performance by 41.5% and 63.8%, and the performance variance (σ2) by 65.7% and 88.0%.

Published in:

SoC Design Conference (ISOCC), 2011 International

Date of Conference:

17-18 Nov. 2011