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Shot-Noise-Induced Failure in Nanoscale Flip-Flops Part II: Failure Rates in 10-nm Ultimate CMOS

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8 Author(s)
Jannaty, P. ; Dept. of Phys., Brown Univ., Providence, RI, USA ; Sabou, F.C. ; Le, S.T. ; Donato, M.
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In part I of this paper, a robust numerical framework based on Markov queueing theory and nonequilibrium Green's functions was presented to model the fluctuations in a CMOS flip-flop, which could potentially give rise to logic upsets. In part II, this framework is used to investigate quantitatively the failure in time for end-of-roadmap CMOS devices at the LG= 10 nm length scale as a function of various parameters such as size, temperature, threshold voltage, process-induced threshold variation, and VDD. It is shown quantitatively that process-induced variation and/or use of ultralow VDD make the devices extremely vulnerable to noise. Higher temperatures give rise to higher failure rates through increased thermal fluctuations and through reduced Ion/Ioff ratios, due to an inverse dependence of the subthreshold slope on temperature. The effect of nonlinear voltage-dependent node capacitors are modeled via the use of arbitrary-shaped queues, and the corresponding results are reported.

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Electron Devices, IEEE Transactions on  (Volume:59 ,  Issue: 3 )