Referenced Items are not available for this document.
A new system for the instruction level timing analysis of hard real time programs is presented. The analysis exploits the very simple structure of these programs, resulting in a considerable processing time improvement compared to general case analysis techniques. The new analysis system covers all speed up mechanisms used for modern superscalar processors at once: pipelining, data caching and instruction caching. The analysis can handle a unified cache as well as separate caches for data and instructions
Published in:
Real-Time Systems, 1997. Proceedings., Ninth Euromicro Workshop on
Date of Conference: 11-13 Jun 1997
- Page(s):
- 80 - 86
- Meeting Date :
- 11 Jun 1997-13 Jun 1997
- Print ISBN:
- 0-8186-8034-2
- INSPEC Accession Number:
- 5659189
- Conference Location :
- Toledo
- Digital Object Identifier :
- 10.1109/EMWRTS.1997.613767
- Product Type:
- Conference Publications
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