By Topic

Methodology for designing partially reconfigurable systems using transaction-level modeling

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)

As a matter of fact, there is a lack of tools handling partially reconfigurable FPGAs modeling at a high level of abstraction that give sufficient degree of freedom to the designer for testing scheduling algorithms. In this paper, we present our methodology to fill this gap and take into account partial reconfiguration into high-level modeling with SystemC. Our approach relies on dynamic threads to change the functionality of modules during runtime and on transaction level modeling for all the communications. We introduce a reconfiguration manager to develop and validate scheduling algorithms for hardware tasks management. Moreover, our simulator performs design space exploration in order to find a viable implementation (in terms of reconfigurable zones) for a given application. Our methodology is validated with the modeling of a dynamically reconfigurable video transcoding chain.

Published in:

Design and Architectures for Signal and Image Processing (DASIP), 2011 Conference on

Date of Conference:

2-4 Nov. 2011