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High speed VLSI architecture for 2-D lifting Discrete Wavelet Transform

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4 Author(s)
A. D. Darji ; Indian Institute of Technology Bombay ; Rajul Bansal ; S. N. Merchant ; A. N. Chandorkar

The lifting scheme reduces the computational complexity for computing Discrete Wavelet Transform (DWT) compared to convolution. We have proposed a high performance and memory efficient architecture with parallel scanning method for 2-D DWT using 5/3 Lifting wavelet. This 2-D architecture is composed with two 1-D DWT units and a Transpose Unit (TU). Proposed parallel scanning reduces requirement of on-chip line buffer compared to other line based scanning. Proposed 2-D DWT architecture utilizes only 2N size buffer for NxN sized image, which is low compare to 3.5N usual requirement for to implement 5/3 Lifting wavelet. This is achieved by performing column and row transform simultaneously. Designed 1-D DWT module can process two inputs at a time and produce two outputs per clock which reduces latency significantly compared to other 2-D dual scan based DWT architectures. Designed TU operates at half clock rate which reduces power and its design is independent of size of input image. Instead of shifter we propose Hardwired Scaling Unit (HSU) for coefficient multiplication. Unlike shift register unit this design saves clocks and helps in reducing power by great amount. This architecture is synthesized using Xilinx ISE 10.1 and is implemented on Virtex-IIPRO XC2VP30 FPGA. Very low FPGA resource utilization is found.

Published in:

Design and Architectures for Signal and Image Processing (DASIP), 2011 Conference on

Date of Conference:

2-4 Nov. 2011