Referenced Items are not available for this document.
This paper describes the implementation of a graphic rendering pipeline on an MPSoC architecture devoted to the dynamic management of static task graphs. It exhibits the highly non stationary workloads of this application domain and provides first useful feedbacks motivating the design of innovative embedded architectures that have to face heterogeneous computation domains such as graphics and telecommunications. Especially these experiments stress the needs for data dependent resource allocation strategies.
Published in:
Design and Architectures for Signal and Image Processing (DASIP), 2011 Conference on
Date of Conference: 2-4 Nov. 2011
- Page(s):
- 1 - 7
- E-ISBN :
- 978-1-4577-0619-6
- Print ISBN:
- 978-1-4577-0620-2
- INSPEC Accession Number:
- 12493448
- Conference Location :
- Tampere
- Digital Object Identifier :
- 10.1109/DASIP.2011.6136864
- Product Type:
- Conference Publications
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