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Fast and accurate hybrid power estimation methodology for embedded systems

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5 Author(s)
Rethinagiri, S.K. ; INRIA Lille Nord Eur., Univ. de Lille 1, Villeneuve-d''Ascq, France ; Ben Atitallah, R. ; Niar, S. ; Senn, E.
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Nowadays, having the appropriate Electronic System Level (ESL) tools for power estimation in embedded systems is becoming mandatory. The main challenge for the design of such dedicated tools is to achieve a better trade-offs between accuracy and speed. In this paper, a new power consumption estimation methodology for embedded systems is proposed. First, the Functional Level Power Analysis (FLPA) is used to set up generic power models based on real board measurements. In the second step, a simulation framework is developed to evaluate accurately the architectural parameters of the elaborated power models. The proposed methodology has several benefits: it improves significantly the accuracy of the functional level approach and the power consumption estimation can be accomplished without a costly and complex material. In order to speed up the estimation process, our methodology refers to the selection of data pattern size and to the application sampling technique. Experimental results show that our tool achieves high simulation speed of 21 times faster with a marginal power estimation error of 1%.

Published in:

Design and Architectures for Signal and Image Processing (DASIP), 2011 Conference on

Date of Conference:

2-4 Nov. 2011