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Morpheo: A high-performance processor generator for a FPGA implementation

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4 Author(s)
Mathieu Rosiere ; UPMC Université Pierre et Marie Curie 4 place jussieu, Paris, France ; Jean-Lou Desbarbieux ; Nathalie Drach ; Franck Wajsburt

Complex applications, such as multimedia, telephony or cryptography, in embedded systems must provide more and more performance that can be achieved by using multiple levels of parallelism. Today, FPGA are viable alternatives for these kinds of applications. Unfortunately, the available processors on FPGA do not provide sufficient performance. This work proposes the Morpheo tool that is a generator of configurable high performance processors dedicated to FPGA. As the FPGA architecture is more restrictive than on ASIC, VHDL models produced by Morpheo can also be used for an ASIC implementation. The main advantage is that there is no need for specific components, therefore, processors are easier to generate. Despite the architectural changes related to the FPGA target, the IPC (Instructions Per Cycle) of 2-way and 4-way superscalar processors are, respectively, 0.81 and 0.74 times that of M5 processors (ASIC targeted) with corresponding parameters. These processors can be placed in a Xilinx Virtex-5 xc5vlx330 using 15% and 31% of hardware available resources and perform at, respectively, 79 MHz and 72 MHz.

Published in:

Design and Architectures for Signal and Image Processing (DASIP), 2011 Conference on

Date of Conference:

2-4 Nov. 2011