With the advances in semiconductor technology, more and more units such as cores, caches, memory controller, and input/output (I/O) can be integrated on a single processor. The latest generation of the IBM System z® *Trademark, service mark, or registered trademark of International Business Machines Corporation in the United States, other countries, or both. processor family exploits these technology capabilities and integrates four cores, along with several cache, memory, and I/O units on a single die. More parallel units not only promise increased throughput but also add significant complexity to all chip-wide functions such as on-chip communication among the units. Many of the System z reliability, availability, and serviceability features are based on chip-wide functions, which are referred to as pervasive functions. Among others, the pervasive functions include chip initialization, test, control of clocks, monitoring of status information, and error reporting during system operation, as well as system reconfiguration while the system is running. As the complexity of many pervasive functions dramatically grows with the increasing number of integrated units, a new modular and scalable architecture for pervasive functions has been developed for the IBM zEnterprise® 196 processor (central processor (CP) chip) and system controller (SC chip) to cope with these challenges. This paper outlines the architecture for the CP and SC chips as they pertain to pervasive design. We discuss the architecture considerations taken when the new pervasive architecture was devised and elaborate on the implementation. Furthermore, we show how the novel pervasive architecture is used for very-large-scale integration testing, how it supports power management features, and how it facilitates a modular firmware design.
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IBM Journal of Research and Development
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23 January 2012
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