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Distributed power network co-design with on-chip power supplies and decoupling capacitors

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2 Author(s)
Selçuk Köse ; Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York 14627 ; Eby G. Friedman

With each technology generation, the power delivery network becomes larger and more complicated, making the system analysis process computationally complex. The rising number of on-chip power supplies and intentional decoupling capacitors inserted throughout an integrated circuit further complicates the analysis of the power distribution network. Interactions among the on-chip power supplies, decoupling capacitors, and load circuitry are investigated in this paper. The on-chip power supplies and decoupling capacitors within the power network are simultaneously co-designed and placed. The effect of physical distance on the power supply noise is investigated. This methodology changes conventional practices where the power distribution network is designed first, followed by the placement of the decoupling capacitors.

Published in:

System Level Interconnect Prediction (SLIP), 2011 13th International Workshop on

Date of Conference:

5-5 June 2011