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Different Si oxide dimension (OD) geometrical features, consisting of Shallow Trench Insulator (STI) structure, and processes of fabrication such as one-side pad SiN layer and two-sides pad SiN layer are implemented to investigate the residual mechanical stress in Si oxide dimension through full process flow of modern semiconductor device. The Raman spectroscopy with polarized incoming laser light and the technology computer aided design (TCAD) simulation tool are used to estimate and extract the stress distribution, which will influence the device performance seriously, along the different axes. A technology computer aided design tool, ANSYS, is upgraded to yield stress fields in the deep submicron complementary metal-oxide-semiconductor devices. From a practical viewpoint in the modem manufacture of semiconductor, it is demonstrated and proposed in this work that the use of one-side Pad-SiN (CVD-SiN) layer and optimum STI/OD structure can allow significant reduction of the compressive stress in the active region, which will enhance the electron mobility, due to the smaller STI trench volume for the filling of compressive-like STI oxide material and suitable stress distribution, respectively.