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A major shift in logic CMOS technology from planar device to multi-channel device is underway in order to continue the device scaling without degrading short-channel effect beyond 30-nm node . A distinct feature of the multi-channel device is that higher channel dimensionality increases the surface-to-body-volume ratio and improves the control of channel potential by the gate. However, the limited depletion charge in the small volume of the body makes it difficult to control threshold voltage (VT) of the device, which also challenges the implementation of the conventional multi-VT library scheme for low power circuit design . A similar problem in FDSOI MOSFET can be handled by the Ground-Plane technique or back-gate scheme proposed by Wong et al. . In this work, we investigate the extension of the scheme to nanowire devices using TCAD simulation. Specially, we focus on the case of Tunnel FET devices which are expected to be promising for sub 20-nm ultra-low power CMOS technology.