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Stability and integration density are two important SRAM performance metrics. A well designed SRAM cell has high stability and high integration density. Stability and integration density are competing parameters. Increasing the stability usually requires increasing the width of the access (AC) transistor, which decreases the integration density. SRAM occupies a high percentage of chip area in modern-day chips. Any method to decrease the cell area increases the integration density of the chip, and potentially decreases the cost. Traditional scaling relied on decreasing the device dimensions by 0.7× to decrease the area by 0.5×. In the recent times, as the gate length (LG) scaling slowed down, techniques like thin-cell layouts and Self-Aligned Contacts (SAC) are used to maintain the area scaling trend . We propose an SRAM cell with Selectively-Recessed Shallow-Trench Isolation (SR-STI) FinFET to improve the stability and decrease cell area.