Compact analytical modeling of the gate leakage current partitioning for Double Gate MOSFET device

In this paper, we have developed and analyzed a compact gate leakage current partitioning model for Nanoscale Double Gate MOSFETs, assuming the gate current is due to direct tunneling. We have considered the cases of one high k dielectric layer (as an ideal case) and two layers (high k dielectric materials as an insulator with a thin layer of SiO
₂
as an interfacial layer). The model calculations show a good agreement with 2D TCAD numerical device simulations (Silvaco ATLAS).