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Compact analytical modeling of the gate leakage current partitioning for Double Gate MOSFET device

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6 Author(s)
Darbandy, G. ; Dept. d''Eng. Electron., Electr. i Autom., Univ. Rovira i Virgili, Tarragona, Spain ; Lime, F. ; Cerdeira, A. ; Estrada, M.
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In this paper, we have developed and analyzed a compact gate leakage current partitioning model for Nanoscale Double Gate MOSFETs, assuming the gate current is due to direct tunneling. We have considered the cases of one high k dielectric layer (as an ideal case) and two layers (high k dielectric materials as an insulator with a thin layer of SiO2 as an interfacial layer). The model calculations show a good agreement with 2D TCAD numerical device simulations (Silvaco ATLAS).

Published in:

Semiconductor Device Research Symposium (ISDRS), 2011 International

Date of Conference:

7-9 Dec. 2011