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A 1.9–3.8 GHz \Delta \Sigma Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency

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2 Author(s)
Jaewook Shin ; Dept. of Electron. Convergence Eng., Kwangwoon Univ., Seoul, South Korea ; Hyunchol Shin

A fast and high-precision all-digital automatic calibration circuit that is highly suited for ΔΣ fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock time over an octave tuning range. A high-speed frequency-to-digital converter (FDC) measures VCO frequency on-chip with a sub-fREF frequency resolution of fREF/k in a time period of k·TREF. The on-chip detected VCO frequency is then used for calibrating the loop bandwidth and the VCO frequency. The loop bandwidth calibration circuit measures the VCO gain KVCO and uses it to precisely control the charge pump current, hence making the loop bandwidth constant. For the VCO frequency calibration, a minimum error code finding block significantly enhances the calibration accuracy by finding the truly closest code to the target frequency. Moreover, this method does not need to activate ΔΣ modulator to achieve sub- fREF calibration resolution, which makes this technique much accurate and faster than the conventional ones. A 1.9-3.8 GHz ΔΣ fractional-N synthesizer is implemented in 0.13 μm CMOS, demonstrating that the loop bandwidth calibration is completed in 1.1-6.0 μs with ±2% accuracy and the VCO frequency calibration is completed in 1.225-4.025 μs, all across the entire octave tuning range.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 3 )