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A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator

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3 Author(s)
Pierce Chuang ; Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada ; David Li ; Manoj Sachdev

A single-cycle 64-bit binary comparator utilizing a radix-2 tree structure is proposed in this brief. This novel comparator architecture is specifically designed for static logic to achieve both low-power and high-performance operation, particularly at low-input data activity environments. This brief presents a detailed performance and power analysis of various state-of-the-art comparator designs across three CMOS technologies. At 65-nm technology, with 25% (10%) data activity, the proposed design demonstrates 2.3 × (3.5 x) and 3.7 × (5.8 x) power and energy-delay product efficiency, respectively. In addition, the proposed work is 2.7 × faster at iso-energy(80 fJ) or 3.3 × more energy efficient at iso-delay(200 ps) than existing designs.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:59 ,  Issue: 2 )