By Topic

A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Chuang, P. ; Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada ; Li, D. ; Sachdev, M.

A single-cycle 64-bit binary comparator utilizing a radix-2 tree structure is proposed in this brief. This novel comparator architecture is specifically designed for static logic to achieve both low-power and high-performance operation, particularly at low-input data activity environments. This brief presents a detailed performance and power analysis of various state-of-the-art comparator designs across three CMOS technologies. At 65-nm technology, with 25% (10%) data activity, the proposed design demonstrates 2.3 × (3.5 x) and 3.7 × (5.8 x) power and energy-delay product efficiency, respectively. In addition, the proposed work is 2.7 × faster at iso-energy(80 fJ) or 3.3 × more energy efficient at iso-delay(200 ps) than existing designs.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 2 )