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Abstract-This paper presents an extremely compact, highly efficient hardware implementation of the Reed Solomon (RS) decoder. Such efficiency is of critical importance for the next generation of passive optical networks featuring bit rates of 10 Gb/s, high bit error rates and high cost sensitivity. RS codes are widely used for error correction in optical communication networks. The central element of a t-error correcting RS decoder is the key equation solver, which is the most time-critical stage in the RS decoder operation. It uses 2t equations to determine up to 2t unknown values. A key equation solver typically performs the Berlekamp-Massey (BM) algorithm or the Modified Euclidean (ME) algorithm. Hardware implementations of these algorithms usually include a large number of Galois Field (GF) multipliers needed to achieve the required throughput. This paper presents a scalable BM architecture and a scalable ME architecture that minimizes the number of GF multipliers by their higher utilization. This is achieved through efficient control that avoids idle cycles and also through optimal grouping of multipliers into parallel structures given the bit error distribution for the respective optical network. The major building block of this architecture is a compact, programmable GF processor (GFP) capable of high frequency operation.