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A Class of Low Power Error Compensation Iterative Decoders

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5 Author(s)
Hussien, A.M.A. ; Univ. of California Irvine, Irvine, CA, USA ; Khairy, M.S. ; Khajeh, A. ; Eltawil, A.M.
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Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we introduce a class of modified Turbo and LDPC decoders that provide significant improvements over standard decoders in the presence of hardware noise. Simulation results show a consistent improvement in the BER performance of the modified decoders across all SNRs with very small area and power overheads as compared to the conventional decoders.

Published in:

Global Telecommunications Conference (GLOBECOM 2011), 2011 IEEE

Date of Conference:

5-9 Dec. 2011

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