By Topic

A fast parallel implementation of Feng-Rao algorithm with systolic array structure

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Chih-Wei Liu ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Kuo-Tai Huang ; Chung-Chin Lu

We develop a parallel implementation of Feng-Rao algorithm (1993) with systolic array architecture by adopting a specially arranged syndrome matrix. The specially arranged syndrome matrix is in a nearly Hermitian or Hankel form. This parallel decoding architecture can correct up to i errors, where t is equal to half of the Feng-Rao bound, and has the time complexity (m+g+1) by using a series of (t+[(g-1)/2]+1) effective processors (or cells) and g trivial processors. The control circuit for the proposed systolic array architecture is quite simple and a circuit for performing the majority voting scheme is also developed. The proposed architecture without inclusion of the majority voting scheme requires totally t+[(g-1)/2] inversion circuits and (t+[(g-1)/2])(t+1+[(g-1)/2])/2 multipliers. In a practical design, this hardware complexity is acceptable

Published in:

Information Theory. 1997. Proceedings., 1997 IEEE International Symposium on

Date of Conference:

29 Jun-4 Jul 1997