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Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm

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4 Author(s)
Negi, K. ; Grad. Sch. of Sci. & Thechnology, Nagasaki Univ., Nagasaki, Japan ; Dohi, K. ; Shibata, Y. ; Oguri, K.

In this paper, deep pipelined FPGA implementation of a real-time image-based human detection algorithm is presented. By using binary patterned HOG features, AdaBoost classifiers generated by offline training, and some approximation arithmetic strategies, our architecture can be efficiently fitted on a low-end FPGA without any external memory modules. Empirical evaluation reveals that our system achieves 62.5 fps of the detection throughput, showing 96.6% and 20.7% of the detection rate and the false positive rate, respectively. Moreover, if a highspeed camera device is available, the maximum throughput of 112 fps is expected to be accomplished, which is 7.5 times faster than software implementation.

Published in:

Field-Programmable Technology (FPT), 2011 International Conference on

Date of Conference:

12-14 Dec. 2011