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A low-cost and high-throughput architecture for H.264/AVC integer transform by using four computation streams

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3 Author(s)
Yuan-Ho Chen ; Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Tsin-Yuan Chang ; Chih-Wen Lu

In this paper, a four paths H.264/AVC integer transform, which employs four computation paths to achieve a high throughput rate and is implemented by a using single one-dimensional (1-D) DCT core with one transpose memory (TMEM) to reduce the area cost, is proposed. The proposed 1-D integer transform can calculate first-dimensional (1st-D) and second-dimensional (2nd-D) transformations simultaneously in four parallel streams. The two-dimensional (2-D) integer transform utilizes a single 1-D transform core and one TMEM. Therefore, a high throughput rate and a low area cost are achieved in the proposed 2-D transform core. To evaluate the circuit performance of the proposed integer transform, the transform core is implemented in a TSMC 0.18-μm CMOS process. The proposed transform core can achieve a high throughput rate of 1 G-pels/s with only 17.7 K gate area.

Published in:

Integrated Circuits (ISIC), 2011 13th International Symposium on

Date of Conference:

12-14 Dec. 2011