By Topic

A 3bit 36GS/s flash ADC in 65nm low power CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Damir Ferenci ; Institute of Electrical and Optical Communications Engineering, University of Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany ; Simon Mauch ; Markus Grözing ; Felix Lang
more authors

A 36GS/s 3bit flash ADC with a large analog input bandwidth is realized in a 65 nm CMOS technology. By employing a fourfold parallelization a high sampling rate is achieved, while a large input bandwidth is maintained. The measured effective resolution is about 2 bit up to 20GHz input signal frequency at a sampling rate of 36GS/s. The power consumption of the ADC core is 2.6W, the core area is 0.16 mm2. The ADC is intended for the cost-effective integration with an equalizer circuit on a single CMOS chip.

Published in:

2011 International Symposium on Integrated Circuits

Date of Conference:

12-14 Dec. 2011