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Parallel background calibration with signal-shifted correlation for pipelined ADC

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3 Author(s)
Kexu Sun ; Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China ; Xuan Wang ; Lenian He

Correlation-based background calibration methods have been used to correct capacitor mismatch and finite opamp open-loop gain errors of pipelined analog-to-digital converter (ADC). However, the correlation takes long time to converge. A novel parallel background calibration for a 14-bit 100Msps ADC with signal-shifted correction is proposed to overcome the above constraint by three means. First, a modified 1.5-bit stage is proposed in order to allow the injection of a large pseudorandom dither without missing code. Second, before correlating the signal, it is divided into 18 sub-ranges via some additional comparators and shifted for the purpose that the error in correlation converges fast. Finally, the front pipeline stages are calibrated simultaneously rather than stage by stage to reduce calibration tracking time constants. In the proposed background calibration, the capacitor mismatch and gain errors in the modified pipeline stage are measured and calibrated as one error. With calibration, the simulations show a signal-to-noise-and-distortion-ratio performance of 77.1 dB and a spurious-free dynamic range performance of 98.2 dB.

Published in:

Integrated Circuits (ISIC), 2011 13th International Symposium on

Date of Conference:

12-14 Dec. 2011

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