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A dynamic comparator with analog offset calibration for biomedical SAR ADC applications

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2 Author(s)
Herath, M.M.J. ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore ; Chan, P.K.

A new ultra-low voltage and power digital comparator using analog offset calibration technique is presented in this paper. The comparator's input transistors are working in subthreshold region for the entire input range and is used as a zero crossing detector for the analog offset calibration technique. Realized using GLOBALFOUNDRIES 0.18μm CMOS process technology, at the voltage supply of 0.7V and 1MHz clock frequency, the standalone comparator dissipates 153nW but increasing to 494nW with calibration function. For voltage supply down to 0.4V and 20 kHz clock, the single comparator dissipates only 8.054nW. The calibration circuit is capable of reducing a 20mV of input-referred dc offset down to 655.3μV, making it suitable for 10-bit biomedical SAR ADC applications.

Published in:
Integrated Circuits (ISIC), 2011 13th International Symposium on

Date of Conference: 12-14 Dec. 2011

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