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Simulation environment for visual prototyping of circuits and systems

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2 Author(s)
Iouliia Skliarova ; DETI/IEETA, University of Aveiro, Aveiro, Portugal ; Valery Sklyarov

The paper presents results in the following two areas: the visual graphical verification of hardware systems and the synthesis of digital circuits from modular, hierarchical, recursive, and parallel specifications. Within these areas a simulation multimedia environment has been developed and used for verification of the proposed methods that are based on new structural models. The applicability of the environment and the methods is demonstrated through examples.

Published in:

2011 International Symposium on Integrated Circuits

Date of Conference:

12-14 Dec. 2011