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A low-power flash analog-to-digital converter (ADC) using logic gates as comparators is presented. The circuit is designed by using 0.35μm CMOS technology. A conversion delay of 12.55ns has been achieved at 200 Mega sample per second (MSPS). The static current consumptions at zero error bit from the power supply and sampled input are 63μA and 93μA respectively. The high speed and low power characteristic make the ADC structure ideal for the high frequency digitally controlled DC-DC converter applications.