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The presented Pre-Error voltage scheme dynamically tunes the supply voltage of digital circuits, according to PVT variations. By exploiting unused timing margin, produced by state-of-the-art worst-case designs, power consumption is minimized. Pre-Error flip-flops detect late-arriving signals in critical paths for the pre-error rate driven voltage adaptation. We use a Markov chain model to describe the voltage scheme analytically and analyze the effect of global and local variations on the closed-loop control. For an arithmetic circuit, synthesized in an industrial 65nm design-flow, an average power saving of 23% is achieved for very low error rates below 1E-11.