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A 0.35 V, 100 MHz, 0.19 μW/MHz, 3-locking-cycle all digital delay locked loop with asynchronous-deskewing technology in 55 nm CMOS technology

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3 Author(s)
Chun-Yuan Cheng ; Dept. of Electr. Eng., Nat. Chung-Cheng Univ., Chiayi, Taiwan ; Jinn-Shyan Wang ; Cheng-Tai Yeh

This paper presents an all digital delay-locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles, and 119μW power dissipation. The ADDLL is fabricated with 55nm CMOS technology, and the active area is only 0.019 mm2.

Published in:

Integrated Circuits (ISIC), 2011 13th International Symposium on

Date of Conference:

12-14 Dec. 2011