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The delay testing of high-speed system integrated circuits is highly complex. Many test challenges are generated from performance testing requirements. The BIST circuit can help solve traditionally slower ATE tester limitations. In this paper, a double edge clipping (DEC) technique is proposed for high-speed performance testing by utilizing a low-price slow-speed ATE. DEC differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. DEC technique uses a lower-speed input clock frequency, then applies internal clipping and a BIST mechanism to adjust clock edges for high-speed circuit functional testing. The postlayout simulations show that the wide-range (26.5%~76%), fine-scale (16ps) duty cycle adjustment technique with high-precision (28ps) calibration circuit is effective for binning performance and high-speed circuit performance testing. Test chips with wireless test system integration are fully validated.