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A 0.5V 25Mpixels/s SVGA 30fps H.264 video decoder chip

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9 Author(s)
Jia-Wei Chen ; Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan ; Pei-Yao Chang ; Keng-Jui Chang ; Tzu-Yuan Kuo
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A sub-threshold voltage, high throughput H.264 video decoder design is proposed for portable applications in this paper. To improve the performance for high throughput rate applications, the computational complexity in H.264 video decoding is optimized in the proposed design. To reduce complexity, both a shared adder-based hardware sharing scheme and an advanced data management scheme are presented. Moreover, to reduce power consumption, both a low area sub-threshold voltage SRAM and a high performance sub-threshold voltage CMOS circuit design scheme are presented. Exploiting all the design techniques, the proposed 90nm 0.5V 25Mpixels/s SVGA 30fps H.264 decoder outperforms the 65nm design at 0.5V through a 31× improvement in throughput.

Published in:

Integrated Circuits (ISIC), 2011 13th International Symposium on

Date of Conference:

12-14 Dec. 2011