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Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

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20 Author(s)
M. Radosavljevic ; Intel Corporation, Technology and Manufacturing Group, Hillsboro, OR 97124, USA ; G. Dewey ; D. Basu ; J. Boardman
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In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (LSIDE) have been fabricated and compared. For the first time, 3-D Tri-gate InGaAs devices demonstrate electrostatics improvement over the ultra-thin (QW thickness, TQW=10nm) body planar InGaAs device due to (i) narrow fin width (WFIN) of 30nm and (ii) high quality high-K gate dielectric interface on the InGaAs fin. Additionally, the 3-D Tri-gate InGaAs devices in this work achieve the best electrostatics, as evidenced by the steepest SS and the smallest DIBL, ever reported for any high-K III-V field effect transistor. The results in this work show that the 3-D Tri-gate device architecture is an effective way to improve the scalability of III-V FETs for future low power logic applications.

Published in:

Electron Devices Meeting (IEDM), 2011 IEEE International

Date of Conference:

5-7 Dec. 2011