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Comprehensive analysis of UTB GeOI logic circuits and 6T SRAM cells considering variability and temperature sensitivity

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4 Author(s)
Hu, V.P.-H. ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Ming-Long Fan ; Pin Su ; Ching-Te Chuang

A comprehensive comparative analysis of leakage-delay, stability and variability of GeOI logic circuits and 6T SRAM cells with respect to the SOI counterparts is presented. The UTB GeOI circuits show better power-performance than the bulk Ge-channel circuits, and preserve the leakage reduction property of stacking devices, while the band-to-band tunneling leakage of bulk Ge-channel devices cannot be reduced by stacking transistors. At Vdd = 1V and 400K, the delays of inverter, dynamic gates, latch and multiplexer for GeOI circuits are smaller than the SOI counterparts. For equal Ion design, the GeOI SRAM cells exhibit better μRSNM/σ RSNM and smaller cell leakage variation at both Vdd = 1V and 0.5V.

Published in:

Electron Devices Meeting (IEDM), 2011 IEEE International

Date of Conference:

5-7 Dec. 2011