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Racetrack memory cell array with integrated magnetic tunnel junction readout

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15 Author(s)
Annunziata, A.J. ; IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA ; Gaidis, M.C. ; Thomas, L. ; Chien, C.W.
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In this paper, we report the first demonstration of CMOS-integrated racetrack memory. The devices measured are complete memory cells integrated into the back end of line of IBM 90 nm CMOS. We show good integration yield across 200 mm wafers. With magnetic field-assist, we demonstrate current-driven read and write operations on cells within a 256-cell CMOS-integrated array.

Published in:

Electron Devices Meeting (IEDM), 2011 IEEE International

Date of Conference:

5-7 Dec. 2011