By Topic

A unified 3D device simulation of random dopant, interface trap and work function fluctuations on high-к/metal gate device

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Yiming Li ; Dept. of Electr. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Hui-Wen Cheng ; Yung-Yueh Chiu ; Chun-Yen Yiu
more authors

In this work, we for the first time estimate total fluctuation resulting from random dopants (RDs), interface trap (ITs) and work functions (WKs) using experimentally calibrated 3D device simulation on 16-nm-gate high-k/metal gate devices. The total 3D simulated threshold voltage fluctuation (σVth), induced by the aforementioned random sources simultaneously, is 55.5 mV for NMOS; however, a statistical total sum of these fluctuations is 12.3% overestimation because independence assumption on random variables is invalid owing to strong interactions among RDs, ITs and WKs. Device's DC/AC and CMOS SRAM circuit fluctuations have similar observation. FinFET-based structure innovation possessing large fluctuation suppression (σVth = 30.2 mV; 45.6% reduction), compared with process efforts on planar one, is further discussed.

Published in:

Electron Devices Meeting (IEDM), 2011 IEEE International

Date of Conference:

5-7 Dec. 2011