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Radiation-hardened phase-locked loop fabricated in 200 nm SOI-CMOS

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7 Author(s)
Matsuura, D. ; Mitsubishi Heavy Ind. Ltd., Komaki, Japan ; Hirose, K. ; Kobayashi, D. ; Ishii, S.
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We designed a phase-locked loop (PLL) operating at 200 MHz using 0.2 μm fully depleted silicon-on-insulator (SOI) technology. By SPICE simulation with an appropriate single-event transient (SET) model, we achieved a radiation-hardened PLL that does not cause a SET upset upon ion irradiation with a linear energy transfer (LET) of 50 MeV-cm2/mg at an areal penalty of 75%.

Published in:

Radiation and Its Effects on Components and Systems (RADECS), 2011 12th European Conference on

Date of Conference:

19-23 Sept. 2011