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Impact of strained-Si PMOS transistors on SRAM soft error rates

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4 Author(s)
Mahatme, N.N. ; Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ. Nashville, Nashville, TN, USA ; Bhuva, B.L. ; Fang, Y.-P. ; Oates, A.S.

For advanced deep sub-micron technology nodes, the use of strained-Si is fast becoming the norm. The experimental Soft Error Rate (SER) of 40 nm technology triple-well SRAMs that incorporate strained-Si PMOS transistors are compared with the SER for 90 nm, 65 nm and 45 nm triple-well bulk CMOS SRAMs fabricated without strain. Results indicate that the total SER decreases by approximately 50% with strain. Most importantly, however, the Multiple-Cell Upset (MCU) Rate decreases significantly. The factors that result in improved SER for strained SRAMs are investigated.

Published in:

Radiation and Its Effects on Components and Systems (RADECS), 2011 12th European Conference on

Date of Conference:

19-23 Sept. 2011